TY  JOUR
TI  Simulation of a cyclic redundant encoder for data transmission  by Ethernet II frames in the Xilinx Vivado environment
KW  cyclic redundant coding
KW  programmable logic integrated circuit
KW  Ethernet
KW  information processing
KW  computing
JO  Vestnik of Astrakhan State Technical University. Series: Management, computer science and informatics
AU  Aminev, D..
AU  Zaharzhevskiy, S..
AU  Kozyrev, D..
AU  Houankpo, H..
PY  2025
IS  2025
PB  Astrakhan State Technical University